Conventionally, as a fault-tolerant storage device, a disk array device of a RAID (Redundant Arrays of Independent Disks or Redundant Arrays of Inexpensive Disks) configuration is known. The disk array device is connected to a host to form a RAID system. In general, in the RAID system, a write-back method is used when data is written in the disk device in response to an I/O request from the host. In the write-back method, upon receipt of the I/O request, requested data is not written in the disk device as a writing destination but is once stored in a cache memory, such as a volatile memory, and a completion response is sent to the host. After that, the data stored in the cache memory is caused to be reflected on the disk device as the writing destination. Therefore, when a power failure occurs, cache data in the cache memory is saved in a nonvolatile memory to prevent the cache data from being lost. Then, upon recovery from the power failure, the cache data saved in the nonvolatile memory is restored in the cache memory (see e.g. Japanese Laid-Open Patent Publication No. 2004-118837).
FIG. 12 illustrates a flow of a conventional power recovery process.
In the disk array device, a data transfer section 920 performs data transfer between a cache memory 910 and a nonvolatile memory 930 according to an instruction from a controller 900 that controls the entire disk array device. The data transfer section 920 includes a write circuit, not illustrated, a read circuit 921, and an erase circuit 922. When a power failure occurs, the write circuit performs a saving process for saving cache data from the cache memory 910 into the nonvolatile memory 930. The saving process requires a backup power supply. To this end, a plurality of write circuits are provided and parallel processing is executed. In the nonvolatile memory 930, a plurality of memory areas having different access ports are provided in a manner associated with the write circuits, respectively. In the illustrated example, there are provided a memory #0 (931) associated with a first access port, and a memory #1 (932) associated with a second access port. The read circuit 921 performs a read process for transferring cache data from the nonvolatile memory 930 to the cache memory 910. The erase circuit 922 performs an erase process for erasing the nonvolatile memory 930. Unless the nonvolatile memory 930 is erased once, it is impossible to write data therein. Therefore, in a cache data recovery process, the read process for transferring cache data saved in the nonvolatile memory 930 to the cache memory 910 and the erase process for erasing the nonvolatile memory 930 are both carried out. It should be noted that DMA (Direct Memory Access) is employed for the processing circuits of the data transfer section 920 due to necessity of performing a high-speed transfer process.
Next, the procedure of the cache data recovery process will be described.
When the disk array device recovers from the power failure, the controller 900 checks a flag to confirm whether or not the disk array device has recovered from the power failure (step S91). If the disk array device has recovered from the power failure, the controller 900 instructs the read circuit 921 to perform a cache recovery process for the memory #0 (931) (step S92). The read circuit 921 reads out the cache data saved in the memory #0 (931), and transfers the cache data to the cache memory 910. This data transfer processing is carried out sequentially from a start address of the memory #0 (931) in units of a predetermined data transfer size. At this time, whenever the data transfer of each unit is terminated, a read address block is set. Then, when the data transfer up to the last address block is completed, a completion notification (#0) is output to the controller 900. Upon receipt of the completion notification (#0), the controller 900 instructs the read circuit 921 to execute a cache recovery process for the memory #1 (932) (step S93). The same process as described above is performed to transfer cache data of the memory #1 (932) to the cache memory 910. When the cache recovery process has been terminated, a completion notification (#1) is delivered to the controller 900. Upon receipt of the completion notification (#1), the controller 900 starts a host I/O request process by write through (step S94). Then, the controller 900 executes a restoration process for writing the cache data in a disk device 940 (step S95). By executing processing thus far, cache data before the power failure is recovered in the cache memory 910.
Subsequently, the erase process is carried out. The controller 900 instructs execution of the erase process for the memory #0 (931) (step S96). In response to this instruction, the erase circuit 922 starts the erase process for the memory #0 (931). After that, the controller 900 instructs execution of the erase process for the memory #1 (932) (step S97). In the erase process as well, it is necessary to set a new address block for each unit of data. After completion of the erase process for all the areas, the erase circuit 922 outputs a completion notification.
After receiving the completion notification of the erase process, the controller 900 starts a host I/O request process by write back (step S98). Then, the controller 900 starts the disk array device (step S99).
In the RAID system, however, it takes long time to complete the conventional cache recovery process, and hence the start-up of the disk array device is delayed after the recovery of power.
As illustrated in FIG. 12, in the power recovery process, also after the cache data is restored in the cache memory 910, unless the erasing of the nonvolatile memory 930 is terminated, the disk array device cannot be started. As a consequence, it takes extra time for the erase process, whereby time necessary for the recovery process becomes very long. For example, if the number of DMA engines of the data transfer section 920 is increased, the speed of the recovery process can be increased. However, this method is not practicable since hardware resources are limited. Further, the controller 900 has to give instructions to the read circuit 921 and the erase circuit 922, which increases load on the recovery process. This also hinders reduction of time for recovery process.
Further, although not illustrated, in the data transfer section 920, to enable detection of errors generated during transfer of data and recovery of data, a redundant code is added to the data every predetermined data length. In the read circuit 921, the redundant code is used for detection and correction of errors. Therefore, the data transfer size is limited to the size of a data length to which the redundant code is added. By increasing the prefetch amount, it is possible to increase the speed of the data transfer processing, but this makes it impossible to correct errors. Therefore, it has been difficult to reduce time for cache data recovery by increasing the prefetch amount.
As described hereinabove, it has been difficult to reduce time necessary for the cache data recovery process performed during recovery from a power failure. This problem has been a major factor causing an increase in the rise time of the disk array device after power recovery.